The present invention relates generally to timing circuits and more particularly relates to a mechanism for measuring the time duration of asynchronous events.
Numerous applications exist that require the measurement of asynchronous events. A common example is the measurement of timing drift between two clock signals as described in the following example. Many communications systems include both active and standby modes of operation. In the active mode, transmission between the two endpoints (e.g., between a master and a slave) may occur. During the standby mode of operation, however, transmission temporarily ceases between the endpoints.
Standby modes are used to significantly reduce the power consumption of communications devices whereby all but a small portion of necessary circuitry is powered down. Standby modes of operation are used extensively in mobile communications devices, especially those powered by batteries or other limited types of power sources. At some point later in time, the device is xe2x80x98awokenxe2x80x99 and returns to the active state for a period of time before entering standby mode again.
A common requirement of communication devices is that while in standby mode the two endpoints need to remain synchronized to a certain extent, such that network timing can be quickly recovered without the need for an extended acquisition phase. Commonly, a device (i.e. typically a portable device based on battery power) switches from a fast clock rate used in the active mode to a lower rate clock while in standby mode, which enables the device to maintain network timing while significantly reducing its power consumption. Since the accuracy, or relative drift, of this slower clock determines the amount of time that the system can remain in standby without actual transmissions being exchanged, it is important to either have an accurate standby clock or to be able to compensate for clock drifts and errors.
In measuring the clock drift of multiple clock signals, the timing of asynchronous events may be required. Often, cascaded flip-flop circuits are used to capture asynchronous events. A common occurrence in these types of circuits is known as the metastability problem wherein one or more flip flops may get confused if the data at the input to the flip flop changes during the setup time interval preceding a clock pulse. The flip flop may make a decision in any case or if the input changed at exactly the wrong time during the moment of decision, such that a decision is not made and the output of the flip flop lingers around the logic threshold for a period of time (i.e. microseconds). In the worst case, the flip-flop settles in a particular state and then switches back to the other state.
Prior art mechanisms intended to reduce the probability of metastability affecting internal logic are based on buffering comprising two or more cascaded synchronized flip-flops, each sampling the output of its predecessor.
Note that in properly designed synchronous systems such problems should not occur as setup times are satisfied by using logic fast enough such that the inputs to flip flops are stable for a period of tsetup before the next clock pulse. Detecting and measuring asynchronous signals going from one clock domain to another, however, is problematic and may lead to metastability problems because it cannot be guaranteed that input transitions do not occur during the setup time interval.
A schematic diagram illustrating a prior art circuit for measuring the time of asynchronous events is shown in FIG. 1. The circuit, generally referenced 10, comprises two flip-flops FF112, FF214 and a counter 16. The asynchronous events are input to the circuit by the binary data signal 20. The events are represented by a low to high transition followed some time later by a high to low transition. A clock signal 18 clocks all three components. The clock rate is assumed to be higher than that of the input data signal.
In operation, the first flip-flop FF1 synchronizes the asynchronous data signal to the clock. The second flip flop FF2 acts as a buffer to prevent any metastability of the signal input to the counter. The output of FF2 enables the counter 16. After the occurrence of a high to low transition of the data signal, the count value represents the duration between the two events.
A problem in this circuit, however, is that FF1 may enter metastability since a transition of the asynchronous input data signal may occur within the setup or hold time of FF1. In this case, the output of FF1 cannot be predicted and may oscillate before settling to a random output of 0 or 1. FF2 buffers the counter from FF1 that may be in metastability. This, however, does not guarantee that the counter will be provided the correct enable signal.
A first timing diagram illustrating the inaccuracies of the prior art circuit of FIG. 1 is shown in FIG. 2. The data signal representing the asynchronous event is approximately two cycles wide and arrives asynchronously with respect to the clock. Due to FF2, the EN signal goes high after a full clock delay. The resultant count represents the length of time between events. Note, however, that the event +/xe2x88x92 a whole clock cycle yields the same count result.
A second timing diagram illustrating the inaccuracies of the prior art circuit of FIG. 1 is shown in FIG. 3. In this example, the data signal is approximately four clock cycles wide. The resultant count output, however, is again two. Here, the resultant error may be as high as two clock cycles. Thus, the prior art circuit 10 has a resultant resolution of two clocks.
The xe2x80x98Base linexe2x80x99 is the xe2x80x98calibration periodxe2x80x99 measured by the counter after averaging the ambiguity originating from FF1/FF2. The error incurred is xc2x1xc2xd clock cycle. The overall xe2x80x98calibration periodxe2x80x99 measurement error is thus xc2x11 fast clock cycle.
A third timing diagram illustrating the inaccuracies of the prior art circuit of FIG. 1 is shown in FIG. 4. The clock 18 is indicated by the fast clock. The data signal, which is four fast clocks wide, is indicated by the slow signal representing the calibration period to be measured. The calibration period in terms of the fast clock is also shown. The resultant counter output is shown. The ambiguity of the slow signal is indicated as +/xe2x88x92xc2xd fast clock, which at the rising and falling edge will yield the same result.
It is important to note that the probability of having a metastable condition on the second flip-flop is highly dependent on the time between the sampling instances at the first stage of the metastability circuit to the sampling at the second stage. In other words, the probability of metastability is inversely proportional to the clock period.
In the case where the sampling of the first stage does not generate a metastability state at its output, the data will be valid at the output of the second stage after the next sampling edge of the second stage. In the case where the first stage sampling does generate a metastability state at its output, there is a probability that by the time the second stage is sampled, the state of the first stage has settled into the state that existed before the sampling.
In this case the data will be valid not after the next sampling edge of the second stage, but after the second sampling edge. This results in an ambiguity as to which edge the data will be valid on at the output of the second stage. The amount of ambiguity is the time difference between the two active sampling edges of the second stage.
In many applications, such as in communication systems (e.g., wired, wireless, portable, etc.), it is desirable to recover and/or measure timing with greater accuracy. There is thus a need for a mechanism for measuring asynchronous events which provides improved accuracy and which reduces the probability of occurrence of metastability conditions in the logic circuitry.
The present invention provides a novel and useful mechanism for measuring the time duration between asynchronous events. The invention has numerous applications including, for example, measuring the relative timing drift of a clock signal. The invention provides improved accuracy with respect to prior art mechanisms and circuits, utilizing a circuit of low complexity and without requiring additional higher frequency clocking signals. The present invention is particularly suitable for incorporation in hardware-based circuits such as those used in portable computing devices such as laptop computers, cellular telephones and wireless connected PDAs.
To aid in illustrating the principles of the present invention, an example application is presented, wherein a period corresponding to the rate of the standby clock of a device is measured using a more accurate faster clock that is used during the active mode of operation of the device. The result of this measurement is used to compensate for drifts and to better time the turn-on of the device after extended standby periods, which are typically measured based on the slower clock.
However, since the two frequencies originate from different clock domains and are not synchronized, metastability could occur during the sampling process in the mechanism that uses both. In accordance therewith, the mechanism of the present invention offers a solution to this problem. The mechanism not only reduces the probability of occurrence of a metastability condition in the system, but also improves the timing accuracy which is crucial in making clock drift measurements.
The current art reduces asynchronous event measurement (e.g., clock drift measurement) timing ambiguity to only half a clock cycle while enabling a synchronous solution whereby all flip flops are clocked off the same clock.
The mechanism utilizes two metastability resolvers, one for detecting the rising edge of the input data signal and one for detecting the falling edge. Each metastability resolver comprises two branches of cascaded flip flops wherein each branch is made of one or more flip flops clocked off the rising edge of a fast clock and one or more flip flops clocked off the falling edge of the fast clock.
Each metastability resolver functions to output an edge event signal and a clock phase signal indicating which edge of the fast clock the rising (or falling) edge of the data signal was closer to. The edge event signals are used to start and stop a counter clocked off the fast clock. The clock phase is used to correct (i.e. compensate) the counter value depending on which half cycle of the fast clock the rising and falling edge of the data signal arrived in.
Benefits of the mechanism of the present invention include (1) enhanced timing resolution of metastability resolving from xc2x11 clock period of the prior art to xc2x1xc2xd clock period, which is advantageous in many portable applications with limited battery power; (2) enabling the extension of standby time in portable wireless devices based on slow standby clocks, which in most cases can be doubled with the use of the mechanism of the present invention; and (3) simple realization of circuitry to implement the invention, resulting in low cost and low current consumption; (4) does not require the use of higher clock rates (which are typically unavailable) to enhance the timing resolution of the device; and (5) use of the same fast clock to drive the circuitry thus allowing the device to remain synchronous.
There is thus provided in accordance with the present invention an apparatus for measuring the time duration between asynchronous events using a first clock comprising means for generating a first edge event signal and an associated first clock phase signal, the first edge event signal corresponding to the detection of a rising edge of an input data signal, the first clock phase signal adapted to indicate whether the rising edge of the data signal occurred in a first or second half cycle of the first clock, means for generating a second edge event signal and an associated second clock phase signal, the second edge event signal corresponding to the detection of a falling edge of the data signal, the second clock phase signal adapted to indicate whether the falling edge of the data signal occurred in a first or second half cycle of the first clock, a counter adapted to generate an N bit output wherein counting is enabled in response to the first edge event signal and wherein counting is disabled in response to the second edge event signal and means for compensating the N-bit counter output in accordance with the first clock phase signal and the second clock phase signal so as to generate an N+1 bit output representing the time duration.
There is also provided in accordance with the present invention a method of measuring the time duration between asynchronous events, the method comprising the steps of generating a first edge event signal and an associated first clock phase signal, the first edge event signal adapted to indicate a first transition of an input data signal from a low to high state, the first clock phase signal adapted to indicate whether the first transition of the data signal occurred in a first or second half cycle of a first clock signal, generating a second edge event signal and an associated second clock phase signal, the second edge event signal adapted to indicate a second transition of the input data signal from a high to low state, the second clock phase signal adapted to indicate whether the second transition of the data signal occurred in a first or second half cycle of a first clock signal, enabling an N-bit counter in response to the first edge event signal, disabling the counter in response to the second edge event signal and compensating the N-bit counter output in accordance with the first clock phase signal and the second clock phase signal so as to generate an N+1 bit output representing the time duration.
There is further provided in accordance with the present invention an apparatus for measuring the relative timing drift between a first clock and a slower second clock comprising means for generating a first edge event signal and an associated first clock phase signal, the first edge event signal adapted to indicate a first transition of the second clock from a low to high state, the first clock phase signal adapted to indicate whether the first transition of the second clock occurred in a first or second half cycle of the first clock, means for generating a second edge event signal and an associated second clock phase signal, the second edge event signal adapted to indicate a second transition of the second clock from a high to low state, the second clock phase signal adapted to indicate whether the second transition of the second clock occurred in a first or second half cycle of the first clock, a counter adapted to generate an N bit output wherein counting is enabled in response to the first edge event signal and wherein counting is disabled in response to the second edge event signal and means for correcting the N-bit counter output in accordance with the first clock phase signal and the second clock phase signal so as to generate an N+1 bit output representing the time duration.
There is also provided in accordance with the present invention an apparatus for measuring the relative timing drift between a first clock and a slower second clock comprising a first metastability resolver clocked by the first clock for generating a first edge event signal and an associated first clock phase signal, the first edge event signal corresponding to the detection of a rising edge of the second clock, the first clock phase signal adapted to indicate whether the rising edge of the second clock occurred in a first or second half cycle of the first clock, a second metastability resolver clocked by an inverted first clock for generating a second edge event signal and an associated second clock phase signal, the second edge event signal corresponding to the detection of a falling edge of the second clock, the second clock phase signal adapted to indicate whether the falling edge of the second clock occurred in a first or second half cycle of the first clock, a counter adapted to generate an N-bit output wherein counting is enabled in response to the first edge event signal and wherein counting is disabled in response to the second edge event signal, a correction circuit adapted to generate a correction factor in accordance with the first clock phase signal and the second clock phase signal and an adder adapted to add a least significant bit to the counter output to yield an N+1 bit value and to generate the sum of the correction factor and the N+1 bit value to yield the relative timing drift between the first clock and the second clock.